Speaker
Dr
Sergey Sergeev
(JINR)
Description
The Fast Forward Detector based Level 0 Trigger system architecture is described. The system must provide fast and effective triggering on nucleus – nucleus collisions at the center of the setup with high efficiency for central and semi-central Au + Au collisions. It should identify z- position of the collision with uncertainty better than 5 cm and an event multiplicity in pseudorapidity interval of 2.7 < |η| < 4.1. The system is modular and consists of two arm signal processors and a vertex processor. FPGAs are widely used.
The arm processor crates are located at both sides of MPD magnet yoke to provide minimal cable length and a vertex processor crate is located at the middle of rack line.
Each arm processor receives information from 80 FFD cells and provides preliminary processing of it. The result of pre-processing is sent to the vertex processor. This information includes multiplicity of hits in FFD cells and a time mark signal of the first hit. The arm processor crate also contains a front-end low voltage power supplies.
The vertex processor performs the final trigger processing including estimation of summary FFD hits multiplicity and estimation of Z-coordinate of interaction.
The vertex and arm processors contain interface modules with optical links.
Since all this equipment is located in the experimental area and it is exposed to high energy particle irradiation having influence to the FPGA configuration RAM, the processor units containing FPGA are equipped with configuration loading modules. These modules have a library of FPGA configuration files on board and they could provide simultaneous reloading of FPGA RAM to all system FPGAs by a single command.
Primary author
Dr
Sergey Sergeev
(JINR)
Co-authors
Mr
Victor Rogov
(JINR)
Dr
Vladimir Yurevich
(JINR)
